SREEP

a tool for shift register equivalents

We made a program called SREEP (Shift Register Equivalents Enumeration and Synthesis Program) to solve the enumeration and synthesis problems for SR-equivalents [2]. SREEP adopts GUI (graphical user interface) for expressing outcome by circuit diagram and table. SR-ID code is introduced to represent the structure of each extended SR uniquely. SREEP can generate all SR-equivalents that satisfy the structure, number of stages, upper and lower limits of the number of feed-forwards/feedbacks, etc.

A. Synthesis for SR-Equivalent Circuits

Given several constraints, SREEP generates SR-equivalent circuits that satisfy the constraints. The constraints are the number of stages or flip-flops, lower and upper limits of each number of feed-forwards, feedbacks, and inverters.

B. State Justification for SR-Equivalent Circuits

Given a k-stage SR-equivalent circuit, SREEP-2 generates equations to obtain state justification sequences for the circuit. From the equations, an input sequence of length k that transfers the circuit to a desired final state can be uniquely computed.

C. State Observation for SR-Equivalent Circuits

Similarly, given a k-stage SR-equivalent circuit, SREEP-2 generates equations to solve state observation problem for the circuit. From the generated equations, the initial state of the circuit can be uniquely computed from the output sequence of length k.

References:

Hideo Fujiwara and Marie E. J. Obien,"Secure and Testable Scan Design Using Extended de Bruijn Graphs," 15th Asia and South Pacific Design Automation Conference (ASP-DAC 2010), pp.413-418, Jan. 2010. [Xplore]
Katsuya Fujiwara, Hideo Fujiwara, Marie Engelene J. Obien, and Hideo Tamamoto, "SREEP: Shift Register Equivalents Enumeration and Synthesis Program for Secure Scan Design," 13th IEEE International Symposium on Design and Diagnosis of Electronic Circuits and Systems (DDECS 2010), pp. 193-196, April 2010. [Xplore]
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "SREEP-2: SR-Equivalent Generator for Secure and Testable Scan Design," 11th IEEE Workshop on RTL and High Level Testing (WRTLT'10), pp. 7-12, Dec. 2010.
Hideo Fujiwara, Katsuya Fujiwara, and Hideo Tamamoto, "Secure Scan Design Using Shift Register Equivalents against Differential Behavior Attack," 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), pp.818-823, Jan. 2011. [Xplore]
Katsuya Fujiwara, Hideo Fujiwara, Marie E. J. Obien, and Hideo Tamamoto, "Enumeration and Synthesis of Shift Register Equivalents for Secure Scan Design," IEICE Trans. on Inf. and Syst., Vol. J93-D, No. 11, pp. 2426-2436, Nov. 2010. (In Japanese)
Katsuya Fujiwara, Hideo Fujiwara, and Hideo Tamamoto, "Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design," IEICE Trans. on Inf. and Syst., Vol. E94-D, No. 7, pp. 1430-1439, July 2011.

Download (freeware)

sreep-dist-20190327.zip - size:49MB, SREEP version 0.20190327

sreep-dist-dictionary-stage6.zip - size:959MB, additional dictionary for 6-stage